Semiconductor memories such as dynamic random access memories have literally millions of memory storage cells. These storage cells are typically fabricated having individual capacitors as the memory elements and include access transistors. The cells are arranged in rows and columns. A memory cell array refers to these cells as they are organized in rows and columns. To ensure that a particular memory device is fully operational, each of the individual memory cells within the device is operationally tested.
As semiconductor memory technology has evolved, the typical memory device has increasingly stored more and more individual memory cells. This increase in the population of memory cells in a memory device has correspondingly increased the possibility of defects within one or more memory cells and has also increased the time required to test all the cells. Therefore, the need for rapidly testing the cells of a memory device has become even more crucial.
However, because the typical memory device has so many individual memory cells, testing each individual cell can be quite time consuming. A typical testing method writes a test bit to a memory cell, reads an output bit from the memory cell, and compares whether the output bit is identical to the test bit. This last step is the error-checking step. If an error is found--i.e., the output bit is not identical to the test bit--then a redundant memory cell is used to replace the defective cell.
Because this testing method is so time consuming, various solutions have been proposed to decrease testing time. One typical solution is to write a test bit to a predetermined number of memory cells concurrently, reading the output bits of the memory cells, compressing the output bits into a compressed bit, and error checking just the compressed bit. If at least one of the predetermined number of memory cells is defective, the compressed bit will be in error.
This solution is typically called data compression test mode. It is less time consuming in that a number of memory cells are tested at one time, as opposed to each memory cell being tested one at a time. A deficiency to data compression test mode, however, is its inefficient redundancy. If error checking the compressed bit fails, then all of the predetermined number of memory cells are replaced with redundant cells. Thus, if the predetermined number of cells is seven, even if only one of the seven cells is defective, all seven cells are replaced by redundant cells. In other words, the fault-isolation capability of the data compression test mode is severely reduced.
Therefore, for the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification as disclosed herein, there is a need for a data compression test mode that provides more efficient redundancy. That is, there is a need for a data compression test mode that replaces only those memory cells that are defective, instead of all of the predetermined numbered of memory cells tested, and thus which provides for a more accurate fault-isolation technique.